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INTEGRATED CIRCUITS
DATA SHEET
SAA2501 Digital Audio Broadcast (DAB) decoder
Preliminary specification File under Integrated Circuits, IC01 January 1995
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
CONTENTS FEATURES 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.17.1 7.17.2 7.17.3 7.17.4 7.18 7.19 7.20 7.20.1 7.20.2 7.20.3 7.20.4 7.20.5 7.20.6 7.20.6.1 7.20.7 7.20.8 7.20.9 7.20.10 7.20.11 7.20.12 APPLICATION GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Coding system Basic functionality SAA2501 clocks Crystal oscillator Clock frequencies when using the slave input Clock frequencies when using the master input Target applications; applying the SAA2501 with 2 ISO/MPEG sources Buffered clock outputs Functionality issues Synchronization to input data bitstreams Master input bit rate selection Sample rate selection Handling of errors in the coded input data sub-band filter signals Baseband audio processing Decoding control signals Coded data interfaces The coded data master input interface The coded data slave input interface Slave input transfer speed of first frame Slave input transfer speed of subsequent frames The sub-band filter interface The baseband output interface The L3 control interface L3 signals L3 transfer types L3 interface initialization at an SAA2501 device reset L3 interface control SAA2501 status Data items General data items SAA2501 settings item Input data frame header items Error report item Audio service synchronized data item Ancillary Data/XPAD item APU coefficients item 7.20.13 7.20.14 8 8.1 8.1.1 8.1.1.1 8.1.1.2 8.1.1.3 8.1.1.4 8.1.2 8.1.3 8.1.3.1 8.1.3.2 8.1.4 8.1.5 8.1.5.1 8.1.5.2 8.1.5.3 8.2 8.2.1 8.2.2 9 10 11 12 13 14 14.1 14.1.1 14.1.2 14.1.3 15 16
SAA2501
Speed limitations of the L3 interface Default item data values after reset APPENDIX Preliminary specification 3-line `L3' interface Introduction Addressing mode Special function operational address Data mode Halt mode Device interface reset Extended addressing Operational address declaration Operational address invalidation Example of a data transfer Timing requirements Addressing mode Data mode Halt mode SAA2501 L3 protocol enhancement options Testing L3RDY by polling L3DATA Options to increase the timing accuracy of the APU coefficient writing LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Plastic quad flat-packs By wave By solder paste reflow Repairing soldered joints (by hand-held soldering iron or pulse-heated solder tool) DEFINITIONS LIFE SUPPORT APPLICATIONS
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
1 FEATURES 2 APPLICATION
SAA2501
* Advanced error protection * Integrated audio post processing for control of signal level and inter-channel crosstalk * Demultiplexing of Program Associated Data (PAD) in the input bitstream * Automatic digital de-emphasis of the decoded audio signal * Separate master and slave inputs * Automatic sample frequency and bit-rate switching in master input mode * Automatic synchronization of input and output interface clocks in master input mode * Selectable audio output precision; 16, 18, 20 or 22 bit * Low power consumption * Decoded sub-band signal and error flag outputs for error concealment. 4 ORDERING INFORMATION
* Digital Audio Broadcast systems as defined in "Eureka 147". 3 GENERAL DESCRIPTION
The SAA2501 audio source decoder supports ISO/IEC MPEG layers I and II and all DAB specific features as described in "Eureka 147 draft specification (EU147)".
PACKAGE TYPE NUMBER NAME SAA2501H Note 1. When using IR reflow soldering it is recommended that the Drypack instructions in the "Quality Reference Handbook" (order number 9398 510 63011) are followed. Supply of this "ISO/IEC 11172-3" audio standard Layer I or layer II compatible IC does not convey a licence nor imply a right under any patent, or any Industrial or Intellectual Property Right, to use this IC in any ready-to-use electronic product. QFP44(1) DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm VERSION SOT307-2
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
5 BLOCK DIAGRAM
SAA2501
FSCLK384
MCLKOUT
FSCLKIN
MCLK24
X22OUT
L3MODE
FSCLKM
MCLKIN
FSCLK
L3DATA
L3CLK
handbook, full pagewidth
5 TDI TDO TCK TMS TRST CDS CDSEF CDSCL CDSWA CDSSY CDM CDMEF CDMCL CDMWS 41 37 39 40 38 19 20 18 21 22 15 14 16 13
34
8
7
4
44
10
9
3
2
42 43
24 25 23
11 12
URDA 1
X22IN
MCLK
V DD1 V DD2
CLOCK GENERATOR
DECODING CONTROL
STOP
RESET
SAA2501
DEQUANTIZATION AND SCALING PROCESSOR SYNTHESYS SUBBAND FILTER BANK AND OUTPUT PROCESSING
INPUT PROCESSOR
26
SD
36 TC0
35 TC1
17 GND2
28 GND3
6 GND1
27 33 31 32 FDEF FDFSY FDAO FDAI
29
30
MBE112
SCK WS
Fig.1 Functional block diagram.
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
6 PINNING SYMBOL RESET FSCLK FSCLKIN MCLK VDD1 GND1 MCLKOUT MCLKIN X22OUT X22IN STOP URDA CDMWS CDMEF CDM CDMCL GND2 CDSCL CDS CDSEF CDSWA CDSSY L3CLK L3DATA L3MODE SD FDEF GND3 SCK WS FDAO FDAI FDFSY VDD2 TC1 TC0 TDO TRST TCK January 1995 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 master reset input sample rate clock output; buffered signal sample rate clock signal input (see Table 1) master clock output; buffered signal supply voltage 1 ground 1 master clock oscillator output master clock oscillator input or signal input 22.579 MHz clock oscillator output 22.579 MHz clock oscillator input or signal input stop decoding input unreliable data input; interrupt decoding coded data (master input) word select output coded data (master input) error flag input ISO/MPEG coded data (master input) coded data (master input) bit clock output ground 2 coded data (slave input) bit clock ISO/MPEG or EU147 (see Table 8) coded data (slave input) coded data (slave input) error flag coded data (slave input) burst window signal coded data (slave input) frame sync L3 interface bit clock input L3 interface serial data input/output L3 interface address/data select input baseband audio ground 3 baseband audio data baseband audio data filter data output filter data input filter data output frame sync supply voltage 2 I2S I2S clock output word select output I2S data output filter data error flag output DESCRIPTION
SAA2501
TYPE I O I O - - O I O I I I O I I O - I I I I I I I/O I O O - O O O I O - I I O I I
do not connect; factory test control 1 input, with integrated pull-down resistor do not connect; factory test control 0 input, with integrated pull-down resistor boundary scan test data output boundary scan test reset input; this pin should be connected to ground for normal operation boundary scan test clock input 5
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
SAA2501
SYMBOL TMS TDI FSCLK384 FSCLKM MCLK24
PIN 40 41 42 43 44 boundary scan test data input
DESCRIPTION boundary scan test mode select input sample rate clock frequency indication input sample rate clock source selection for the master input master clock frequency indication input
TYPE I I I I I
43 FSCLKM
44 MCLK24
FSCLK384
38 TRST
40 TMS
37 TDO
39 TCK
36 TC0
41 TDI
dbook, full pagewidth
35
42
34
V DD2
TC1
RESET FSCLK FSCLKIN MCLK VDD1 GND1 MCLKOUT MCLKIN X22OUT X22IN STOP
1 2 3 4 5 6 7 8 9 10 11
33 FDFSY 32 FDAI 31 FDAO 30 WS 29 SCK
SAA2501
28 GND3 27 FDEF 26 SD 25 L3MODE 24 L3DATA 23 L3CLK
URDA 12
CDMWS 13
CDMEF 14
CDM 15
CDMCL 16
GND2 17
CDSCL 18
CDS 19
CDSEF 20
21
CDSSY 22
MBE113
Fig.2 Pin configuration (QFP44). 7 7.1 FUNCTIONAL DESCRIPTION Coding system For layers I and II of ISO/MPEG the broadband audio signal spectrum is split into 32 sub-bands of equal bandwidth. For each sub-band signal a masking threshold is calculated. The sub-band samples are then re-quantized to such an accuracy that the spectral distribution of the re-quantization noise does not exceed the masking threshold. It is this reduction of representation accuracy which yields the data reduction. The re-quantized sub-band signals are multiplexed, together with ancillary information regarding the actual re-quantization, into a MPEG audio bitstream.
The perceptual audio encoding/decoding scheme defined within the "ISO/IEC 11172-3 MPEG Standard" allows for a high reduction in the amount of data needed for digital audio whilst maintaining a high perceived sound quality. The coding is based upon a psycho-acoustic model of the human auditory system. The coding scheme exploits the fact that the human ear does not perceive weak spectral components that are in the proximity (both in time and frequency) of loud components. This phenomenon is called masking. January 1995 6
CDSWA
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
During decoding, the SAA2501 de-multiplexes the MPEG audio bitstream, and with knowledge of the ancillary information, reconstructs and combines the sub-band signals into a broadband audio output signal. 7.2 Basic functionality
SAA2501
configure the SAA2501, to read its decoding status, to read Program Associated Data, and so on. Several pins are reserved for Boundary Scan Test and Scan Test purposes. 7.3 SAA2501 clocks
From a functional point of view, several blocks can be distinguished in the SAA2501. A clock generator section derives the internally and externally required clock signals from its clock inputs. The SAA2501 can switch between a master and a slave input interface to receive the coded input data. The input processor parses and de-multiplexes the input data stream. The de-quantization and scaling processor performs the transformation and scaling operations on the sample representations in the input bitstream to yield sub-band domain samples. The sub-band samples are transferred via an external detour to the synthesis sub-band filter bank processor. The detour can be used to process the decoded audio in the sub-band domain. The baseband audio samples, reconstructed by the sub-band filter bank, can be processed before being output. The decoding control block houses the L3 control interface, and handles the response to external control signals. The L3 control interface enables the application to
The SAA2501 clock interfacing is designed for application versatility. It consists of 10 signals (see Table 1). From a functional point of view, the clock generator inside the device can be represented as shown in Fig.3. As described above, the SAA2501 incorporates a master input interface on which it requests for coded input data itself, as well as a slave input interface for an imposed coded data input bitstream. The input interface is selected with flags MSEL0 and MSEL1, controlled via the L3 microcontroller interface. Depending on the selected input interface, only a limited number of the three possible input clocks (MCLKIN, X22IN and FSCLKIN) is actually required. The various clock options are selected with the 3 external control signals MCLK24, FSCLKM and FSCLK384. These control signals must be stationary while the device reset signal at pin RESET is de-activated; changing any of these 3 signals without simultaneously resetting the SAA2501 can result in malfunctioning.
Table 1
Clock interfacing signals DIRECTION input output output input master clock oscillator output master clock output; buffered signal master clock frequency indication input: MCLK24 = 0; MCLKIN frequency is 12.288 MHz (256 x 48 kHz) MCLK24 = 1; MCLKIN frequency is 24.576 MHz (512 x 48 kHz) FUNCTION master clock oscillator input or signal input
SIGNAL MCLKIN MCLKOUT MCLK MCLK24
X22IN X22OUT FSCLKIN FSCLK FSCLK384
input output input output input
22.5792 MHz (512 x 44.1 kHz) clock oscillator input or signal input 22.5792 MHz (512 x 44.1 kHz) clock oscillator output sample rate clock signal input sample rate clock signal input; buffered signal sample rate clock signal frequency indication input: FSCLK384 = 0; FSCLKIN frequency is 256fs FSCLK384 = 1; FSCLKIN frequency is 384fs
FSCLKM
input
sample rate clock source selection when using the master input: FSCLKM = 0; use MCLKIN or X22IN as source FSCLKM = 1; use FSCLKIN as source
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Preliminary specification
Digital Audio Broadcast (DAB) decoder
SAA2501
handbook, full pagewidth
MCLK24
control
MCKDIS (L3)
MCLK 12.288 or 24.576 MHz OSC 2 C = 48 kHz 3 X22OUT X22IN OSC 22.5792 MHz 256f s or 384f s control 2 C = 32 kHz C = 44.1 kHz C in CONTROL out DIVIDER
internal master clocks
MCLKIN MCLKOUT
decoded sample rate index
256f s C=0 C=1 C
FSCLKIN FSCLKM
1
FCKENA (L3)
FSCLK FSCLK384 control 256f s or 384f s
C
C=0 C=1
4
SCK
64f s 00 fs
6
WS
64 A A=B B to input interfaces
0: use master input 1: use slave input
MSEL1
MSEL0 (L3)
MGB491
Italics: internal signal designation.
Fig.3 SAA2501 clock generator.
7.4
Crystal oscillator
The recommended crystal oscillator configuration is shown in Fig.4. The specified component values only apply to crystals with a low equivalent series resistance of <40 .
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
SAA2501
handbook, full pagewidth
C2 10 C1 X1 R1 9 R2 8 C3 X2 R4 7 C4 R3
MBE114
SAA2501
C1 = C2 = 33 pF; R1 = R4 = 1 M; R2 = R3 = 1 k; X1 = 22.5792 MHz; X2 = 24.5760 MHz or 12.2880 MHz The specified component values only apply to crystals with a low equivalent series resistance of <40 .
Fig.4 Crystal oscillator components. The main advantage of this configuration is that the SAA2501 determines automatically which sample rate is active from the sampling rate setting of the input data bitstream, and then selects either MCLKIN or X22IN as the clock source for the I2S clocks SCK and WS. This configuration is therefore particularly suited in applications with more than one possible sample rate setting. 2. If FSCLKM = 1, the configuration is comparable to the configuration when using the slave input (see Section 7.5). MCLKIN and FSCLKIN are used as the clock sources, and X22IN is not required. MCLKIN may again have a frequency of 12.288 MHz (indicated by MCLK24 = 0) or 24.576 MHz (indicated by MCLK24 = 1), and FSCLKIN may have a frequency of 256 times (indicated by FSCLK384 = 0) or 384 times (indicated by FSCLK384 = 1) the sample frequency of the input data. MCLKIN and FSCLKIN do not have to be phase or frequency locked. 7.7 Target applications; applying the SAA2501 with 2 ISO/MPEG sources
7.5
Clock frequencies when using the slave input
If the slave input is used (MSEL1 and MSEL0 = 10 or 11), the SAA2501 clock sources are MCLKIN and FSCLKIN and X22IN is not used. The I2S clocks SCK and WS are generated by the SAA2501 from FSCLKIN. FSCLKIN may be designated to have a frequency of 256 times (indicated by FSCLK384 = 0) or 384 times (indicated by FSCLK384 = 1) the sample frequency of the coded input data. Master clock signal MCLKIN may be chosen to have a frequency of 12.288 MHz (indicated by MCLK24 = 0) or 24.576 MHz (indicated by MCLK24 = 1). MCLKIN and FSCLKIN do not have to be phase or frequency locked. If the application is based on a sample frequency of 48 kHz or 32 kHz, and a sample rate related clock of 12.288 MHz (256 x 48 kHz; 384 x 32 kHz) is available, this can be taken advantage of by using this signal for both MCLKIN and FSCLKIN. 7.6 Clock frequencies when using the master input
If the master input is used (MSEL1 and MSEL0 = 00), one out of two configurations is selected with signal FSCLKM with respect to the clock sources: 1. If FSCLKM = 0, MCLKIN and X22IN are the clock sources. FSCLKIN is not used in this configuration. FSCLK384 must be set to logic 0 for reasons of internal connections in the clock generator circuitry. MCLKIN may have only frequency 24.576 MHz (so mandatory accompanied by MCLK24 = 1), and X22IN must have a frequency of 22.5792 MHz. MCLKIN and X22IN do not have to be phase or frequency locked. January 1995 9
In Table 2 the three target applications of the SAA2501 are summarised. The slave input application is labelled S, and the master input applications are labelled M0 and M1.
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
Table 2 Target applications APPLICATION ATTRIBUTE CONDITIONS SLAVE INPUT INPUT INTERFACE FSCLKM MCLKIN X22IN FSCLKIN FSCLK Notes 1. FSCLKIN must be locked to input data clock CDSCL; see Section 7.17.2. 2. FSCLKIN is not used, but FSCLK384 must be LOW. 3. Must be electrically defined; e.g. LOW. Sections 7.5 and 7.6 explain which clock sources are activated by the SAA2501 depending on the selected input interface. This automatic clock source selection makes it easy to apply the SAA2501 in systems with two ISO/MPEG coded data sources (one connected to the master input, an one to the slave input), even if these data sources use different clocks. 7.8 Buffered clock outputs FSCLK384 = 1 FSCLK384 = 0 FCKENA = 1 (L3) MCLK24 = 1 MCLK24 = 0 CONDITIONS S(1) X 24.576 MHz 12.288 MHz note 3 384fs 256fs copy of FSCLKIN
SAA2501
MASTER INPUT M0(2) 0 24.576 MHz illegal 22.579 MHz illegal note 3 256fs M1 1 24.576 MHz 12.288 MHz note 3 384fs 256fs copy of FSCLKIN
decoding process, as well as the audio post-processing features, offered by the SAA2501, are described in more detail in Section 7.10. 7.10 Synchronization to input data bitstreams
The SAA2501 provides a signal MCLK which is a buffered version of MCLKIN. MCLK can be set to 3-state by setting the L3 control interface flag MCKDIS to 1 in applications where MCLK is not needed. Signal FSCLK is copied from the FSCLKIN input for application types S and M1 or generated with a frequency of 256fs by the SAA2501 for application type M0. After a device reset, FSCLK must be enabled explicitly by setting L3 flag FCKENA, or can alternatively be left 3-stated in applications where it is not needed. After a device reset, MCLK is enabled; FSCLK is disabled (i.e. both MCKDIS and FCKENA are set to logic 0). 7.9 Functionality issues
After a reset, the SAA2501 mutes both sub-band and baseband audio data. After data inputting has started, the SAA2501 searches either for a sync pattern or a sync pulse. The speed at which input data is read by the master input to search for synchronization is described below. If the application is such that the SAA2501 starts at a random moment in time compared to the bitstream, maximal one frame is skipped before a synchronization pattern or pulse is encountered. When the SAA2501 has detected the first synchronization word or pulse, a number of frames are decoded in order to verify synchronization; the input data for these frames is read and decoded, but meanwhile the audio output is muted. The number of muted frames depends on the input data format (ISO/MPEG or EU147), whether the ISO/MPEG Cyclic Redundancy Check (CRC) is active, and whether the bit rate is free format. If the synchronization is found to be false, the SAA2501 resumes the initial synchronization as described above. If the detected pulse/pattern is concluded to be a real synchronization pulse/pattern, Table 3 indicates the number of muted frames.
The SAA2501 fully complies with ISO/MPEG layer I and II and EU147 with the slave input. With the master input, the SAA2501 complies with ISO/MPEG layer I and II, excluding the free format bit rate. Several aspects of the
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
Table 3 Muted frames MINIMUM NUMBER OF MUTED FRAMES DURING SYNCHRONIZATION CRC FREE FORMAT BIT RATE No CRC CRC 2 1 NON-FREE-FORMAT BIT RATE 1 0 7.11 Master input bit rate selection
SAA2501
As explained in Section 7.10, the SAA2501 can be used to alternate between two applications: one with the slave input, and one with the master input. When using the master input, the SAA2501 should fetch data with the effective bit rate, but cannot know what the bit rate of the input data is until it has established synchronization. To overcome this paradox, the input requesting is done at the last selected bit rate. After a device reset, the master input bit rate selection defaults to the value indicated in Table 4.
Table 4
Defaults master input bit rate FSCLK384 0 0 1 0 1 0 1 FSCLKIN X(1) 256 x 32 kHz 384 x 32 kHz 256 x 44.1 kHz 384 x 44.1 kHz 256 x 48 kHz 384 x 48 kHz 417.96 384 DEFAULT MASTER INPUT BIT RATE (kbits/s) 384 278.64
FSCLKM 0 1
Note 1. X = don't care. When FSCLKM = 0, the default master input bit rate is 384 kbits/s. When FSCLKM = 1, the SAA2501 uses signal FSCLKIN to derive the selected bit rate, but it has no indication concerning the sample rate corresponding to FSCLKIN. Therefore, a bit rate of 384 kbits/s is selected at an assumed sample rate of 44.1 kHz; with other sample rates, the bit rate changes proportionally. The consequence is that while the SAA2501 synchronises (e.g. after a device reset), the application must at least be able to supply at the given default bit rate the required number of frames plus one additional frame (because of the random decoding start point in the input bitstream). Buffers in the application must thus be chosen sufficiently large to prevent under or overflows. The speed with which input data is requested by the master input is changed by the SAA2501 in each of the following cases: 1. When input synchronization is established after checking a number of frames and the bit rate index of the newly decoded bitstream indicates a different bit rate than that currently selected. In this event, the bit rate is adapted to the newly decoded index. January 1995 11 2. When the active input interface is changed from the master to the slave input, or the signal STOP is activated; in these events input requesting stops. 3. When the active input interface is changed from the slave to the master input, or the signal STOP is deactivated; the bit rate is set to the last selected master input bit rate (the last selected master input bit rate is memorised while using the slave input). In all other events (e.g. when the SAA2501 goes and stays out of synchronization), the data requesting speed of the master input is maintained. 7.12 Sample rate selection
When using the slave input, or when using the master input with FSCLKM = 1, the application must know the sample rate: FSCLKIN must be applied, which has a frequency which is a multiple of the sample rate; the (sample rate dependent) I2S timing signals SCK and WS are generated from FSCLKIN. These configurations will normally be used in applications with a fixed sample rate. Should the sample rate change, then the SAA2501 must be reset.
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
When using the master input with FSCLKM = 0, the SAA2501 selects the active sample rate autonomously, and generates the signals SCK and WS from its crystal clocks. After a device reset, the SAA2501 selects a sample rate of 44.1 kHz by default. SCK and WS may, and will only, show phase or frequency changes in any of the following 3 situations: 1. When the SAA2501 establishes synchronization with the coded data input bitstream. 2. When the active input interface is changed from the master input with FSCLKM = 0 to the slave input (i.e. the timing source for the generation of SCK and WS is switched from the crystal clocks to FSCLKIN). 3. When the active input interface is changed from the slave input to the master input with FSCLKM = 0 (i.e. the timing source for the generation of SCK and WS is switched from FSCLKIN to the crystal clocks); the sample rate is set to the last selected sample rate that was used with the master input (the last selected sample rate is memorized while using the slave input). In all other cases, SCK and WS keep on running without phase or frequency changes, and the sample rate selection remains unchanged. 7.13 Handling of errors in the coded input data
SAA2501
allocation or scale factor select information field in a frame (then the SAA2501 will mute) or inside the scale factor field (then the previous scale factor will be copied). Errors in other data fields are not handled explicitly. If the ISO/MPEG CRC is active, only the CRC result is interpreted: CDSEF/CDMEF un-reliability indications for bit allocation and scale factor select information are neglected. In applications where the ISO/MPEG CRC is always present, the protection bit (which itself is not protected) in the ISO/MPEG header may be overruled by making L3 settings flag CRCACT HIGH. In this manner, the SAA2501 is made robust for data errors on the protection bit. 7.14 Sub-band filter signals
The decoded sub-band signals are output, together with an error indication so that concealment can be applied externally. The optionally concealed sub-band signals are put back into the SAA2501 for synthesis filtering. 7.15 Baseband audio processing
The SAA2501 can handle errors in the input data. Errors are assumed to be present in 3 events: 1. If errors are indicated with the coded input data error flag CDSEF and/or CDMEF. 2. On CRC failure if ISO/MPEG error protection is active. 3. If input bitstream syntax errors are detected. Errors in the input data have an effect on the decoding process if the corrupted data is inside the header, bit
The baseband audio de-emphasis as indicated in the ISO/MPEG input data is performed digitally inside the SAA2501. The incorporated `Audio Processing Unit' (APU) (see Fig.5) can be used to apply inter-channel crosstalk or independent volume control per channel. The APU attenuation coefficients LL, LR, RL and RR may be changed dynamically by the host microcontroller, writing their 8-bit indices to the SAA2501 over the L3 control bus. The coefficient changes become effective within one sample period after the coefficient index writing. To avoid clicks at coefficient changes, the transition from the current attenuation to the next is smoothed. The relation between the APU coefficient index and the actual coefficient (i.e. the gain) is given in Table 5.
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
Table 5 APU coefficient index and actual coefficient APU COEFFICIENT
C - ----2 12 C - 32 - ---------------6
SAA2501
APU COEFFICIENT INDEX C BINARY 00000000 to 00111111 01000000 to 01111110 01111111 1XXXXXXX DECIMAL 0 to 63 64 to 126
From Table 5 we learned that up to coefficient index 64 the step size is approximately -0.5 dB per coefficient increment, and from coefficient index 64 to index 126 the step size is approximately -1 dB per increment. Note that the APU has no built-in overflow protection, so the application must take care that the output signals of the APU cannot exceed 0 dB level. For an update of the APU coefficients, it may be required to increase some of the coefficients and decrease some others. The APU coefficients are always written sequentially in the fixed sequence LL, LR, RL and RR. Therefore, to prevent internal APU data overflow due to non-simultaneous coefficient updating, the following steps can be followed: 1. Write LL, LR, RL, RR once, but change only those coefficients that must decrease; overwrite the coefficients that must increase with their old value (so do not change these yet). 2. Write LL, LR, RL, RR again, but now change those coefficients that must increase, keeping the other coefficients unchanged.
2 127 128 to 255
0 reserved
left decoded handbook, halfpage audio samples LR LL
left output audio samples
RL right decoded audio samples right output audio samples
MGB493
RR
The consequence of this two-pass coefficient updating is that the application must keep a shadow of the current APU coefficients (the L3 APU coefficients data item is write-only).
Fig.5 Audio Processing Unit (APU).
handbook, full pagewidth
APU coefficient index 0 0 64 126 127
32 (1) gain (dB)
(2)
94
MGB494
(1) Step -0.5 dB per coefficient increment. (2) Step -1 dB per coefficient increment.
Fig.6 Relation between APU coefficient index and gain.
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
7.16 Decoding control signals
SAA2501
The decoding is performed by 3 signals as shown in Table 6. Table 6 Signals for decoding control DIRECTION FUNCTION(1) reset SAA2501 to default state input input stop decoding unreliable input data; interrupt decoding
de-activated again. Then the SAA2501 mutes, meanwhile searching for a frame sync pattern or frame sync pulse (the synchronization mode is selected via the L3 control bus) at the input. If synchronization is found, the SAA2501 starts producing output data. The maximum response time to the activation of signal STOP is half a sample period; the re-synchronization time after STOP going LOW again differs in various situations. An `unreliable data' indication can be given to the SAA2501 by making signal URDA HIGH. URDA, like STOP, mutes the sub-band signals and forces the SAA2501 out of synchronization. However, in contrast to STOP, master input data requesting continues at the bit rate that was decoded before URDA became active. The maximum response time to URDA is half a sample period. 7.17 Coded data interfaces
SIGNAL RESET STOP URDA
The master reset signal RESET forces the SAA2501 into its default state when HIGH. RESET must stay HIGH during at least 24 MCLKIN periods if MCLKIN has frequency of 24 MHz (i.e. MCLK24 = 1) or 12 MCLKIN periods if MCLKIN has a frequency of 12 MHz (MCLK24 = 0). At a reset, the SAA2501 synchronization to the input bitstream is lost, the sub-band filter and baseband audio output signals are muted, and the SAA2501 settings are initialized. The decoding can be stopped by making input signal STOP HIGH. Stopping the decoding forces the SAA2501 to end decoding of input data, yet feeding zeroed sub-band samples to the synthesis sub-band filter bank to create a soft muting. When using the master input, input requesting is also stopped. CDMWS stays in its current state while STOP is asserted. The SAA2501 assumes the input synchronization to be lost when the decoding is stopped, thus causing re-synchronization when STOP is
The SAA2501 contains: * A coded data master input interface * A coded data slave input interface (designed for EU147 format). 7.17.1 THE CODED DATA MASTER INPUT INTERFACE
When using the master input, the SAA2501 requests for input data. With the master input, the coded input data may not use the ISO/MPEG free format bit rate or be in EU147 format. The coded data master input interface consists of 4 signals (see Fig.7).
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
Table 7 Signals of coded data master input interface SIGNAL CDM CDMEF CDMCL CDMWS input input output output DIRECTION FUNCTION ISO/MPEG coded input data (master input) coded data (master input) error flag coded data (master input) bit clock coded data (master input) word select
SAA2501
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1 CDM
2
16
17
n
1
2
CDMCL
CDMWS
CDMEF
1 unreliable data bit (example)
MGB495
valid data
valid but unreliable data
invalid data
Fig.7 Input data serial transfer format (master input).
Data clock CDMCL is being output, having a fixed frequency of 768 kHz. Signal CDM carries the coded data in bursts of 16 valid bits. Coded data input frames may only start either at the first or at the ninth bit of a 16 bit valid data burst (i.e. only at a byte boundary). The value of word select signal CDMWS is changed every time new input data is needed: one CDMCL period after each transition in CDMWS, 16 bits of valid data are read serially. Assume N is the number of CDMCL periods between two transitions of CDMWS, and R is the number of CDMCL periods to obtain the effective bit rate E (in kbits/s) at a transferring 16 x 768 data rate of 768 kbits/s, i.e. R = ---------------------- . The SAA2501 E
keeps N close to R, but N can vary plus or minus two: N {round(R)-2,...,round(R)+2}. Error flag CDMEF is used to indicate input data insecurities (e.g. due to erratic channel behaviour). In Fig.7, an example with one unreliable bit is shown. The value of CDMEF may vary for each valid data bit, but is combined by the SAA2501 for every group of 8 input bits. 7.17.2 THE CODED DATA SLAVE INPUT INTERFACE
The coded data slave input interface signals are shown in Fig.8. The coded data master input interface consists of 5 signals (see Table 8).
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Digital Audio Broadcast (DAB) decoder
Table 8 Signals of coded data slave input interface DIRECTION input input input input input FUNCTION ISO/MPEG or EU147 coded input data (slave input) coded data (slave input) error flag coded data (slave input) bit clock coded data (slave input) burst window signal coded data (slave input) frame sync
SAA2501
SIGNAL CDS CDSEF CDSCL CDSWA CDSSY
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frame start CDS
CDSCL
CDSWA
CDSSY
CDSEF
1 unreliable data bit (example)
MGB496
valid data
valid but unreliable data
invalid data
CDSSY indicates frame start during valid data.
Fig.8 Input data serial transfer format (slave input).
CDS is the SAA2501 input data bitstream. Data clock CDSCL must have a frequency equal to or higher than the bit rate. The maximum CDSCL frequency is 768 kHz. Error flag CDSEF is handled in the same way as CDMEF is handled for the master input (in Fig.8, one unreliable data bit is shown as an example). The value of CDSEF is neglected for those bits where CDSWA is LOW. Window signal CDSWA being HIGH indicates valid data; in this way, burst input data is allowed. The constraints for the ability to use `burst signals' are explained later in this Section 7.17.2. Frame sync signal CDSSY indicates the start of each input data frame. CDSSY is synchronous with CDSCL. CDSSY may be present or not: as described later
in this Section 7.17.2. The first valid CDS bit after a leading edge of CDSSY is interpreted to be the first frame bit. The minimum time for CDSSY to stay HIGH is one CDSCL period; the maximum HIGH period is constrained by the requirement that CDSSY must be LOW at least during one CDSCL period per frame (a leading edge, i.e. a frame start indication, must be present every frame). Leading edges of CDSSY can occur while CDSWA is HIGH, as in Fig.8. Alternatively, a situation as shown in Fig.9 is also allowed, where CDSSY has a leading edge while CDSWA is LOW, i.e. during invalid data. The first CDS bit after CDSWA going HIGH is now interpreted to be the first frame bit.
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Digital Audio Broadcast (DAB) decoder
SAA2501
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frame start CDS
CDSCL
CDSWA
CDSSY
MGB497
valid data
invalid data
CDSSY indicates frame start at next valid data.
Fig.9 Input data serial transfer format (slave input).
Whether frame sync signal CDSSY is present or not must be selected with L3 settings flags MSEL1 and MSEL0 (see Section 7.20.7). With respect to the presence of CDSSY, two situations can be distinguished: 1. For EU147 coded input data CDSSY is mandatory. 2. For ISO/MPEG input data if CDSSY is supplied, CDSWA may change each CDSCL period. 3. If CDSSY is not supplied, CDSCL must have a frequency higher than the bit rate (i.e. CDSWA cannot be continuously HIGH), and CDSWA HIGH periods may have only lengths of a multiple of 8 CDSCL periods: data is input in byte bursts. Furthermore, these bursts must be byte aligned with the frame bounds: frames are only allowed to start at the 1st, 9th, 17th etc. bit in a valid data burst. For applications where data is input in bursts of exactly one frame, and where CDSCL has a higher frequency than the bit rate, CDSWA and CDSSY may be interconnected. 7.17.3 SLAVE INPUT TRANSFER SPEED OF FIRST FRAME
The data transferring of the first ISO/MPEG or EU147 frame after starting to decode is shown in Fig.10. It shows the transferring of n-frame bits in one frame between time 0 and t, where t corresponds to 384 sample periods (ISO/MPEG layer I input data) or 1152 sample periods (ISO/MPEG layer II input data). Buffer margin B equals 16 bytes (128 bits). In Fig.10 an effective transferring characteristic is drawn, representing any of the possible ISO/MPEG bit rates. However, input data may be transferred at a higher-than-effective speed (in other words: CDSCL may have a higher frequency than the effective bit rate) in periods during which CDSWA is HIGH, interleaved with invalid data periods where CDSWA is LOW. In the example of Fig.9 this is used to transfer the data of the frame in two bursts, as shown by the actual transferring characteristic. The actual transferring characteristic has a slope equal to the CDSCL frequency while CDSWA is HIGH, and is horizontal during the periods in which CDSWA is LOW (no bits are being transferred).
Both the average and the instantaneous speed at which data is transferred to the slave input interface are limited.
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Digital Audio Broadcast (DAB) decoder
SAA2501
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MGB498
transferred input frame bits n
slope: maximum input bit rate
(1) B B
slope: CDSCL frequency
slope: effective input bit rate (2) (3) 0 t time
B B
(1) The actual transferring characteristics of all frames are restricted to this area. (2) Effective transferring characteristic (example). (3) Actual transferring characteristic of the first frame (example).
Fig.10 Slave input data transferring for the first frame.
The shaded area in Fig.10 represents the restrictions to the actual transferring characteristic of all frames. The actual transferring characteristic may not undercut the effective transferring characteristic by more than B bits to avoid an input underflow. On the other hand, the actual transferring characteristic may not cross the shown upper limit of the shaded area to prevent an input buffer overflow. The slope of this upper limit is determined by the maximum effective input bit rate (depending on the input data format). Table 9 summarizes the slopes as determined by the bit rates supported by ISO/MPEG and EU147. Table 9 Slopes determined by bit rates supported by ISO/MPEG and EU147 EFFECTIVE INPUT BIT RATE (kbits/s) 13.3(1) to 448 3.5(1) to 384 TRANSFERRING UPPER LIMIT SLOPE (kbits/s) 448 384
transmitted (this means using single channel mode, no CRC and 32 kHz sample rate). 7.17.4 SLAVE INPUT TRANSFER SPEED OF SUBSEQUENT
FRAMES
The SAA2501 starts decoding as soon as enough data of the first ISO/MPEG or EU147 input data frame has been received. Thus the start moment of decoding depends on the actual transferring characteristic of the first frame. Decoding start times of subsequent input data frames are also governed by this initial start time. For this reason the transferring characteristic of all subsequent frames must approximate the characteristic of the first frame within the buffer margin B. For the example shown in Fig.10, subsequent frames must be transferred within the shaded area shown in Fig.11.
ISO/MPEG AND EU147 LAYER ISO/MPEG layer I ISO/MPEG layer II Note
1. Achieved using the free format option and the minimum amount of the side information that must be January 1995 18
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Digital Audio Broadcast (DAB) decoder
SAA2501
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MGB499
transferred input frame bits n slope: CDSCL frequency (3)
(1) B B slope: effective input bit rate (2)
B B 0 t time
(1) The actual transferring characteristics of all subsequent frames are restricted to this area. (2) Effective transferring characteristic (example). (3) Actual transferring characteristic of the first frame (example).
Fig.11 Slave input data transferring for subsequent frames, referenced to the first frame.
Note that the actual transferring characteristics of all frames must also remain inside the shaded area of Fig.11. 7.18 The sub-band filter interface
As mentioned earlier, decoded signals in the sub-band domain (before synthesis filtering) are available externally for processing. The associated interface has an I2S-like format (see Fig.12). The filter data interface uses 6 signals as shown in Table 10.
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Digital Audio Broadcast (DAB) decoder
SAA2501
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MSB 1
left sample 2
LSB 24
25
26
32
MSB 1
right sample 2
FDAO
FDAI
SCK
WS
valid data
undefinied data
sub-band 0 WS L R L
1 R
2
30
31
0
1
FDFSY
MLC400
Fig.12 Filter data serial transfer format.
Table 10 Signals of filter data interface SIGNAL FDAO FDEF FDAI SCK WS FDFSY DIRECTION output output input output output output filter data output filter data error flag filter data input (optionally processed) filter data (output/input common) bit clock; I2S clock output filter data (output/input common) word select; I2S filter data output frame synchronization The MSB of a sample follows one SCK period after each transition in WS. The 8 unused bits between individual samples in FDAO are zero (SCK is used for the baseband audio output interface as well). The optionally processed sub-band data signal is fed back as input FDAI in a similar format as FDAO, but now the 8 unused bits between individual samples are undefined; they are neglected by the SAA2501. A leading edge in signal FDFSY indicates the start of each FDAO frame. The length of each FDFSY pulse is one sample period; FDFSY is HIGH during a S[0,L] and S[0,R] FUNCTION
Two sub-band samples (one per channel) are transmitted per sample period with output FDAO. The transmission pattern of the samples S [sb, ch] (sb: sub-band index; ch: channel) is: S [0, L], S [0, R], S [1, L], S [1, R],..., S [31, R], S [0, L], S [0, R], etc. Word select signal WS indicates the channel of each sample (WS is also used for the baseband audio output interfacing). The sub-band sample bit clock SCK has a frequency of 64 times the sample frequency. The sub-band samples are transmitted in 24 bit two's complement Pulse Code Modulation (PCM) form, MSB first. Thus, of the available 32 FDAO bits per sample per channel, only 24 are used. January 1995 20
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Digital Audio Broadcast (DAB) decoder
pair. Signal FDEF being HIGH indicates muting of FDAO due to input data errors (see Fig.13). FDEF can only change value at each FDFSY leading edge, i.e. after each 384 sample periods (ISO/MPEG layer I input data) or 1152 sample periods (ISO/MPEG layer II input data): only whole frames are marked to be correct or muted. As shown in detail in Fig.13, transitions of FDFSY and FDEF take place one SCK period before a trailing edge of WS. The optionally processed sub-band data FDAI must be synchronous to SCK and WS. Furthermore, the sub-band index of the FDAI samples must be synchronized to
SAA2501
FDFSY: a sub-band logic 0 sample pair must be input when FDFSY is HIGH (as shown in Fig.12). This means that the delay of the external processing is allowed to be any integer multiple of 32 sample periods. If no external processing is to be applied, FDAO must be input back directly to FDAI. 7.19 The baseband output interface
The decoded baseband audio data is output in an I2S-like format (see Fig.14). The output interfacing consists of 3 signals (see Table 11).
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1 WS
2
3
4
384 (layer I) 1152 (layer II)
1
2
FDFSY
FDEF
WS
WS
FDFSY
FDFSY
FDEF
FDEF
SCK
SCK
MLC401
Fig.13 Filter data error flag (FDEF) timing.
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Digital Audio Broadcast (DAB) decoder
SAA2501
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left sample MSB SD 1 SCK 16/18/20/22 32 LSB
right sample MSB LSB
1
16/18/20/22
32
WS
MGB502
valid data
Fig.14 Baseband output data serial transfer format.
Table 11 Signals of output interfacing SIGNAL SD SCK WS DIRECTION output output output FUNCTION baseband audio data data clock word select
the programming sections a general transfer protocol outline is presented. In Section 8.2 several optional protocol enhancements are given, which on the one hand are less transparent from the applicant's point of view, but on the other hand increase the efficiency of the L3 interfacing. 7.20.1 L3 SIGNALS
The frequency of clock SCK is 64 times the sample frequency (SCK is also used for the sub-band filter interface). The signal SD is the serial baseband audio data, sample by sample (left/right interleaved; the left sample and the right immediately following it form one stereo pair). 32 bits are transferred per sample per channel. The samples are transmitted in two's complement, MSB first. The output samples are rounded to either 16, 18, 20 or 22 bit precision, selectable by the host with L3 control interface flags RND1 and RND0. The remainder of the 32 transferred bits per sample per channel are zero. The word select signal WS indicates the channel of the output samples (LOW if left, HIGH if right); WS is used for the sub-band filter interface as well. If indicated in the coded input data, de-emphasis filtering is performed digitally on the output data, thus avoiding the need of analog de-emphasis filter circuitry. 7.20 The L3 control interface
The L3 protocol uses 3 signals (see Table 12). Table 12 Signals of L3 protocol SIGNAL L3DATA L3CLK L3MODE DIRECTION input/output input input FUNCTION L3 interface serial data L3 interface bit clock L3 interface address/data select
The signals operate according to the L3 protocol description. After each device reset, the L3 interface of the SAA2501 must be initialised and as a consequence, the L3 interface cannot be used while the device reset signal is activated.
The SAA2501 uses the L3 protocol with the associated bus as the control interface with an optional host microcontroller (see Chapter 8 for more information). In January 1995 22
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Digital Audio Broadcast (DAB) decoder
7.20.2 L3 TRANSFER TYPES
SAA2501
The L3 protocol enables the reading and writing of control, status and data. In the L3 protocol, the host first issues an 8 bit wide `operational address' on L3DATA while keeping L3MODE LOW. All devices connected to the L3 bus read the operational address. Next, data transfers from or to the host are done while keeping L3MODE HIGH. The devices Table 13 L3 operational address. 7 0 Note 6 1 5 1 4 0
with an L3 operational address differing from the issued one must ignore these data transfers until the next operational address is issued. Only the device with an address equal to the issued operational address performs the transfer. The SAA2501 has the L3 operational address as shown in Table 13.
3 0
2 0
1 DOM1(1)
0 DOM0(1)
1. The `Data Operation Mode' bits DOM1 and DOM0 determine the mode in which the SAA2501 L3 interface will stay until the next time an L3 operational address is issued (see Table 14). Table 14 DOM1 and DOM0 bits DOM1 0 0 1 1 DOM0 0 1 0 1 TRANSFER TYPE write item data read item data write control to SAA2501 read SAA2501 status corresponding control byte to the SAA2501 first. Next, the item data itself is transferred, always as an integer number of bytes. The status of the SAA2501 can be read via L3. The SAA2501 status flag L3RDY must be monitored before transferring data item bytes to avoid transferring bytes faster than the L3 interface of the SAA2501 can handle. 7.20.3 L3 INTERFACE INITIALIZATION AT AN SAA2501
DEVICE RESET
Control bytes can be written to the SAA2501. Data is transferred to or from the SAA2501 in so-called data items. The items can be a readable or writeable type. A data item transfer is initiated by writing the
Figure 15 shows the mandatory actions that must be taken for correct L3 interface start-up at a device reset.
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RESET
L3MODE
L3CLK 1 2 3
MGB503
Fig.15 L3 interface initialization procedure.
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The actions shown in Fig.15 are: 1. In order for the SAA2501 to keep L3DATA in 3-state, L3MODE must be kept LOW during the whole period that reset signal at pin RESET is asserted; meanwhile, no transfers can be performed (L3CLK stays HIGH). 2. For a proper initialization of the L3 interface logic of the SAA2501, it is mandatory to make L3MODE HIGH and LOW again after the device reset has been de-activated. This must be done before any L3 transfer, even to or from other devices than the SAA2501, is performed. Figure 14 shows that L3CLK stays HIGH during this step. 3. Now the first transfer can be performed on the L3 bus. This transfer must be a operational address (indicated in Fig.14 by L3MODE = 0), addressing any of the devices connected to the L3 bus. The first transfer to the SAA2501 itself must always be either the writing of a control word or the reading of the SAA2501 status; the first transfer may never be a data item byte transfer. Table 15 L3 control 7 CTRL7 6 CTRL6 5 CTRL5 4 CTRL4 3 CTRL3 2 CTRL2 1 CTRL1
SAA2501
Remark: any deviation from these steps may result in illegal L3 protocol behaviour of the SAA2501, even with the possibility of disturbing transfers to other devices connected to the L3 bus. 7.20.4 L3 INTERFACE CONTROL
The control of the SAA2501 L3 interface is performed with one-byte control words. Status polling is not necessary before writing control bytes. After writing the SAA2501 `write control' operational address, one or more control bytes may be written. Each written control byte overrules the previously sent control byte.
0 CTRL0
The definitions of the control bytes (CTRL7 to CTRL0) are given in Table 16. Table 16 Explanation of control bytes CTRL7 TO CTRL0 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 to 11111111 Note 1. Control bytes of type I initiate the transfer of a data item. The control byte of type C may be used after interrupting a transfer, in order to write APU coefficients, to return to the interrupted transfer. DEFINITION read/write SAA2501 settings item read decoded frame header item read used frame header item read error report item reserved read Ancillary Data item write APU coefficients item continue previous transfer reserved TYPE(1) I I I I I I I C -
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7.20.5 SAA2501 STATUS
SAA2501
The host can check the status of the SAA2501 by reading the one-byte status word. After writing the SAA2501 `read status' operational address, the status byte may be read an arbitrary number of times. If status is read more than once, it is updated by the SAA2501 between the individual readings. The status flags of the SAA2501 have the definition as shown in Table 17. Table 17 Status flag definitions 7 DST2(1) Notes 1. By interpreting DST2 to DST0, the host can synchronize to the input frame frequency, and also determine at which moment which L3 data item is available to be read. The value of DST2 to DST0 is only valid if flag INSYNC is set. a) DST2 is a modulo 2 frame counter, i.e. DST2 inverts at the moment the decoding of a new frame is started. DST2 enables to host to sample the decoding subprocess DST1 to DST0 less frequently, meanwhile enabling the host to see if it missed a state. b) DST1 and DST0 values are explained in Table 18. 2. INSYNC is synchronization indication: a) INSYNC = 0; the SAA2501 is not synchronized to the input data. b) INSYNC = 1; the SAA2501 is synchronized to the input data. 3. As indicated in Section 7.20.8, some of the readable data item bits only have significance if INSYNC = 1. 4. L3RDY is L3 interface ready indication: a) L3RDY = 0; the L3 interface cannot perform a new item data transfer yet. b) L3RDY = 1; the L3 interface is ready for the next item data transfer. After a device reset, L3RDY is cleared and will only become set after writing the first L3 control byte to the SAA2501. The value of L3RDY can be tested by polling signal L3DATA instead of transferring the whole status byte. Table 18 Status bytes DST1 and DST0 DST1 0 0 1 1 DST0 0 1 0 1 FUNCTION subprocess 0; reading Ancillary Data or decoding header subprocess 1; decoding bit allocation or scale factor select information subprocess 2; decoding scale factors subprocess 3; decoding samples 6 DST1(1) 5 DST0(1) 4 undefined 3 undefined 2 undefined 1 INSYNC(2)(3) 0 L3RDY(4)
The DST1 and DST0 values in general do not have a determined duration. However, subprocess 3 takes at least 1 a frame period when ISO/MPEG layer I data is decoded, and 5 of a frame period when ISO/MPEG layer II data is 2 6 decoded. Table 19 indicates the validity of the SAA2501 readable data items with respect to the decoding subprocess. Reading of a data item in a period when it is not valid renders undefined data.
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Digital Audio Broadcast (DAB) decoder
SAA2501
Table 19 Validity of SAA2501 readable data items with respect to the decoding subprocess (notes 1 and 2) SAA2501 IS DECODING FRAME n DST2 = 0; SUBPROCESS 0 not valid - - Notes 1. The Table shows following: a) The received Ancillary Data that was multiplexed in frame n-1 becomes valid after subprocess 0 of frame n, and may be read during subprocesses 1, 2 and 3 of frame n. b) The decoded and used frame headers for frame n become valid after subprocess 0 of frame n, and may be read during subprocesses 1, 2 and 3 of frame n. c) Flag BALOK for frame n in the error report item becomes valid after subprocess 1 of frame n, and may be read during subprocesses 2 and 3 of frame n and subprocess 0 of frame n+1. d) Flag DECFM for frame n in the error report item becomes valid after subprocess 2 of frame n, and may be read during subprocesses 3 of frame n and 0 of frame n+1. 2. Note that during subprocess 3 all data items can be read. 7.20.6 DATA ITEMS initiated by writing the corresponding type I control byte (see Section 7.20.4) to the SAA2501. The transfer of every subsequent item data byte must be preceded by reading the status until status flag L3RDY (see Section 7.20.5) is HIGH. L3RDY may be tested alternatively by polling L3DATA, avoiding the need to transfer the whole status byte. Status polling is not required while transferring the APU coefficients item. Table 20 shows an example of how bytes `DDDDDDDD' of a 2 byte data item, with the corresponding control byte `CCCCCCCC', can be read. The writing of item data bytes occurs in a similar way. not valid 1 2 3 0 not valid - - not valid Ancillary Data item (frame n - 1) frame header items (frame n) SAA2501 IS DECODING FRAME n + 1 DST2 = 1; SUBPROCESS 1 - - - not valid 2 - - - - 3
error report: BALOK (frame n) not valid error report: DECFM (frame n)
Data can be transferred to or from the SAA2501 in data items. This section describes the general protocol to accomplish item data transfer, followed by the individual SAA2501 data items. Optional enhancements on the general protocol are described in Chapter 8 Section 8.2.
7.20.6.1
General data items
The data items of the SAA2501 are transferred (i.e. read or written, depending on whether the data item is of readable or writeable type) in bytes. A data item transfer is
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Digital Audio Broadcast (DAB) decoder
Table 20 Example of a 2 byte data item L3DATA(1) 01100010 CCCCCCCC 01100011 SSSSSSSS 01100001 DDDDDDDD 01100011 SSSSSSSS 01100001 DDDDDDDD Note 1. Explanation of bytes: a) CCCCCCCC = control byte. b) SSSSSSSS = status byte. c) DDDDDDDD = data byte. TRANSFER SOURCE host host host SAA2501 host SAA2501 host SAA2501 host SAA2501 L3MODE 0 1 0 1 0 1 0 1 0 1 EXPLANATION indicates `write control' transfer write transfer initiating (type I) control byte indicates `read status' transfer read status (repeat step 4 until L3RDY = 1) indicates `read item data' transfer read first item data byte indicates `read status' transfer read status (repeat step 8 until L3RDY = 1) indicates `read item data' transfer read second item data byte
SAA2501
Each data item has its own length in bytes. It is allowed to transfer less bytes than the data item length, skipping the last one or more bytes (it is even allowed to transfer no bytes at all). It is not allowed to transfer more bytes than the item length. This restriction does not hold for the APU coefficient item. After writing all APU coefficients (i.e. after writing all APU coefficient item bytes), they may be rewritten by continuing writing bytes to the APU coefficient item. Writing more than the specified number of bytes to a writeable data item or writing bytes to a read-only data item may cause the SAA2501 to malfunction. The reading of a write-only data item yields irrelevant data.
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7.20.7 SAA2501 SETTINGS ITEM
SAA2501
The SAA2501 is configured with the SAA2501 settings. The initial value of the SAA2501 settings after reset is all zeros. Table 21 SAA2501 settings item; 1 byte (read/write) 7 MSEL1(1) Notes 1. MSEL1 and MSEL0; these bits select the used input interface, the input data format and the input synchronization type (see Table 22). 2. CRCACT; automatic/forced CRC activity: a) CRCACT = 0; the SAA2501 uses the protection bit in the ISO/MPEG frame header to determine the presence of the CRC. b) CRCACT = 1; the SAA2501 assumes the CRC always to be present. The protection bit in the used ISO/MPEG frame header is forced to 0. 3. MCKDIS; buffered master clock MCLK disabling: a) MCKDIS = 0; enable MCLK. b) MCKDIS = 1; disable (3-state) MCLK. 4. FCKENA; buffered 256fs or 384fs output signal FSCLK enabling: a) FCKENA = 0; disable (3-sate) FSCLK. b) FCKENA = 1; enable FSCLK. 5. SELCH2; with dual channel mode input data (with other modes of input data `don't care': a) SELCH2 = 0; select channel I. b) SELCH2 = 1; select channel II. 6. RND1 and RND0; these bits select the rounding of the baseband audio output samples (see Table 23). Table 22 MSEL1 and MSEL0 MSEL1 0 0 1 1 MSEL0 0 1 0 1 USED INPUT INTERFACE master EU147 slave slave INPUT SYNCHRONIZATION to ISO/MPEG synchronization pattern to synchronization signal CDSSY to ISO/MPEG synchronization pattern to synchronization signal CDSSY 6 MSEL0(1) 5 CRCACT(2) 4 MCKDIS(3) 3 FCKENA(4) 2 SELCH2(5) 1 RND1(6) 0 RND0(6)
Table 23 RND1 and RND0 RND1 0 0 1 1 RND0 0 1 0 1 16 bits 18 bits 20 bits 22 bits OUTPUT SAMPLE ROUNDING LENGTH
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7.20.8 INPUT DATA FRAME HEADER ITEMS
SAA2501
Information about the input data, derived by the SAA2501 from the input data frame headers, may be read from the frame header items. Both the frame header bytes decoded from the input bitstream and the header bytes used for the actual decoding may be read. The decoded frame header item is valid independent of the value of status flag INSYNC, it e.g. shows the decoded
headers while the SAA2501 is in the process of synchronizing. The used frame header item is only valid if status flag INSYNC is set. The used header bytes are derived by the SAA2501 from the decoded header bytes by overruling NOPR to 0 if settings bit CRCACT = 1, and overruling detected errors.
Table 24 Decoded input data frame header item; 3 bytes (read-only) SUBSEQUENT BYTES Decoded header byte 1 Decoded header byte 2 Decoded header byte 3 7 SY3(1) BR3(6) MOD1(8) 6 SY2(1) BR2(6) MOD0(8) 5 SY1(1) BR1(6) 4 SY0(1) BR0(6) 3 ID(2) FS1(7) COPR(10) 2 LAY1(3) FS0(7) ORIG(11) 1 LAY0(4) undefined EMPH1(12) 0 NOPR(5) undefined EMPH0(12)
MODX1(9) MODX0(9)
Table 25 Used input data frame header item; 3 bytes (read-only) SUBSEQUENT BYTES Used header byte 1 Used header byte 2 Used header byte 3 7 1 BR3(6) MOD1(8) 6 1 BR2(6) MOD0(8) 5 1 BR1(6) 4 1 BR0(6) 3 1 FS1(7) 2 1 FS0(7) ORIG(11) 1 LAY0(4) undefined 0 NOPR(5) undefined
MODX1(9) MODX0(9) COPR(10)
EMPH1(12) EMPH0(12)
Notes to "Table 24" and "Table 25" 1. SY3 to SY0; last 4 bits of the synchronization word. For ISO/MPEG only; undefined for EU147 input data. 2. ID; algorithm identification. For ISO/MPEG only; undefined for EU147 input data. 3. LAY1; layer Most Significant Bit (MSB). For ISO/MPEG only; undefined for EU147 input data. 4. LAY0; layer Least Significant Bit (LSB). When decoding EU147 input data these bits are undefined in the decoded header byte and equal 0 in the used header byte. 5. NOPR; CRC on header, bit allocation and scale factor select information activity flag. When decoding EU147 input data these bits are undefined in the decoded header byte and equal 0 in the used header byte. 6. BR3 to BR0; bit rate index. 7. FS1 and FS0; sample rate index. 8. MOD1 and MOD0; mode. 9. MODX1 and MODX0; mode extension. 10. COPR; copyright flag. 11. ORIG; original or home copy flag. 12. EMPH1 and EMPH0; audio de-emphasis, these bits are only meant to monitor the current de-emphasis mode; the corresponding de-emphasis is performed by the SAA2501 automatically before the baseband audio signal is output. January 1995 29
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
7.20.9 ERROR REPORT ITEM
SAA2501
The validity of bit allocation plus scale factor select information and the result of the scale factor CRCs (the latter only when decoding EU147 input data) may be read from the error report item. The error report item is only valid if status flag INSYNC is set. Table 26 Error report item; 1 byte (read-only) SUBSEQUENT BYTES Error report Notes 1. BALOK; bit allocation and scale factor select information validity indication: a) BALOK = 0; bit allocation or scale factor select information are incorrect, or the CRC (if active) over header, bit allocation and scale factor select information fail. b) BALOK = 1; bit allocation or scale factor select information are correct, and the CRC (if active) over header, bit allocation and scale factor select information passes. 2. DECFM; frame skipping/decoding indication: a) DECFM = 0; the current input data frame is skipped, and the corresponding baseband audio output frame is muted due to input data errors or inconsistencies. However, synchronization to the input data is maintained. b) DECFM = 1; the current frame is decoded normally. 3. SFnOK is invalid when decoding ISO/MPEG input data. When decoding EU147 input data: a) SFnOK = 0; then one or more scale factors have been concealed in sub-band block (n). b) SFnOK = 1; no scale factors in sub-band block (n) are concealed (i.e. the error checking has passed). Blocks 0 to 3 are explained in Table 27. Table 27 Content of blocks 0 to 3 BLOCK 0 1 2 3 SUB-BANDS 0 to 3 4 to 7 8 to 15 16 to 31 7 6 5 4 undefined 3 SF3OK(3) 2 SF2OK(3) 1 SF1OK(3) 0 SF0OK(3)
BALOK(1) DECFM(2) undefined
7.20.10 AUDIO SERVICE SYNCHRONIZED DATA ITEM When decoding EU147 input data, the Audio Service Synchronized Data (ASSD), which is contained in each frame, may be read. The subsequent ASSD bytes are read in reverse order with respect to the input bitstream; the first ASSD item byte is the last byte in the input bitstream. The ASSD item is only valid when the status flag INSYNC is set.
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Preliminary specification
Digital Audio Broadcast (DAB) decoder
Table 28 ASSD item; 2 bytes (read-only) SUBSEQUENT BYTES ASSD bytes 1 and 2 7 bit 7 6 bit 6 5 bit 5 4 bit 4 3 bit 3 2 bit 2 1
SAA2501
0 bit 0
bit 1
The ASSD item and the (extended) Program Associated Data [(X)PAD] item (see Section 7.20.11) may be read together as a single item. 7.20.11 ANCILLARY DATA/XPAD ITEM The last 54 bytes of each ISO/MPEG frame, which may carry Ancillary Data (AD), are buffered by the SAA2501 to be read by the host. The subsequent Ancillary Data bytes are read in reversed order with respect to their order in the input data bitstream. The first item data byte is the last frame byte in the input bitstream. The Ancillary Data item is refilled at every frame. The host must either know or determine itself how many of the Ancillary Data bytes are valid per frame. The Ancillary Data item only has significance if status flag INSYNC is set. Table 29 Ancillary Data item; 54 bytes (read-only) SUBSEQUENT BYTES AD byte 1 to AD byte 54 7 bit 7 6 bit 6 5 bit 5 4 bit 4 3 bit 3 2 bit 2 1 bit 1 0 bit 0
Likewise, when EU147 input data is being decoded, the PAD and XPAD bytes contained in each frame may be read, with the 2 PAD bytes first, followed by a maximum of 52 XPAD bytes. The subsequent PAD and XPAD bytes are read in reversed order with respect to their order in the input data bitstream. The first item data byte is the last PAD byte in the input bitstream. The host must determine itself how many of the XPAD bytes are valid per frame by interpretation on the PAD. The (X)PAD item only contains significant data if status flag INSYNC is set. Table 30 (X)PAD item; 54 bytes (read-only) SUBSEQUENT BYTES PAD byte 1 PAD byte 2 XPAD bytes 1 to 52 7 bit 7 bit 7 bit 7 6 bit 6 bit 6 bit 6 5 bit 5 bit 5 bit 5 4 bit 4 bit 4 bit 4 3 bit 3 bit 3 bit 3 2 bit 2 bit 2 bit 2 1 bit 1 bit 1 bit 1 0 bit 0 bit 0 bit 0
7.20.12 APU COEFFICIENTS ITEM The APU coefficients are set by writing their 8 bit indices to the 4-byte APU coefficient item. Only the 7 LSBs are valid. The MSB must be zero. At a device reset, indices LL and RR are set to 00000000 (`no attenuation') and indices LR and RL to 01111111 (infinite attenuation; no crosstalk).
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Preliminary specification
Digital Audio Broadcast (DAB) decoder
Table 31 APU coefficients item; 4 bytes (write-only); see note 1 SUBSEQUENT BYTES APU coefficient LL APU coefficient LR APU coefficient RL APU coefficient RR Note 7 0 0 0 0 6 LL.6 LR.6 RL.6 RR.6 5 LL.5 LR.5 RL.5 RR.5 4 LL.4 LR.4 RL.4 RR.4 3 LL.3 LR.3 RL.3 RR.3 2 LL.2 LR.2 RL.2 RR.2 1
SAA2501
0 LL.0 LR.0 RL.0 RR.0
LL.1 LR.1 RL.1 RR.1
1. Multiple options are supplied by the SAA2501 to increase the timing accuracy of the APU coefficient writing (see Section 8.2). 7.20.13 SPEED LIMITATIONS OF THE L3 INTERFACE When reading the status of, or writing control bytes to the SAA2501, no status polling is necessary, so the speed of these transfers is only limited by the maximum frequency of signal L3CLK and the timing constraints of the L3 protocol. When reading or writing data item bytes, status polling is necessary. In addition to the speed limitation this poses, the application must take precautions that individual data item bytes are transferred at an interval of at least 200 s. Neither the status polling nor a minimum interval between transfers is required when transferring the APU coefficient item. 7.20.14 DEFAULT ITEM DATA VALUES AFTER RESET At a device reset, the L3 interface initialization procedure must be followed. All writeable data items are pre-loaded with a defined default value after the device reset signal has been de-activated. These default values are summarized in Table 32.
Table 32 SAA2501 settings item; default value after device reset (notes 1 to 6) SUBSEQUENT BYTES SAA2501 settings Value Notes 1. MSEL1 = 0 and MSEL0 = 0; the master input is selected. The SAA2501 synchronizes to the ISO/MPEG synchronization pattern. 2. CRCACT = 0; the SAA2501 uses the protection bit in the ISO/MPEG frame header to determine if the CRC is active. 3. MCKDIS = 0; the buffered master clock output MCLK is enabled. 4. FCKENA = 0; the buffered 256fs or 384fs clock output is disabled. 5. SELCH2 = 0; when decoding input data with dual channel mode, channel I is output on both baseband audio output channels. 6. RND1 = 0 and RND0 = 0; the baseband audio output signals are rounded to 16 bit. 7 MSEL1 0 6 MSEL0 0 5 CRCACT 0 4 MCKDIS 0 3 FCKENA 0 2 SELCH2 0 1 RND1 0 0 RND0 0
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Preliminary specification
Digital Audio Broadcast (DAB) decoder
Table 33 APU coefficients item; default values after device reset SUBSEQUENT BYTES APU coefficient LL(1) APU coefficient APU coefficient LR(2) RL(3) 7 0 0 0 0 6 LL.6 = 0 LR.6 = 1 RL.6 = 1 RR.6 = 0 5 LL.5 = 0 LR.5 = 1 RL.5 = 1 RR.5 = 0 4 LL.4 = 0 LR.4 = 1 RL.4 = 1 RR.4 = 0 3 LL.3 = 0 LR.3 = 1 RL.3 = 1 RR.3 = 0 2 LL.2 = 0 LR.2 = 1 RL.2 = 1 RR.2 = 0 1
SAA2501
0 LL.0 = 0 LR.0 = 1 RL.0 = 1 RR.0 = 0
LL.1 = 0 LR.1 = 1 RL.1 = 1 RR.1 = 0
APU coefficient RR(4) Notes
1. LL = 00000000; no attenuation in the left-to-left APU path. 2. LR = 01111111; infinite attenuation in the left-to-right APU path. 3. RL = 01111111; infinite attenuation in the right-to-left APU path. 4. RR = 00000000; no attenuation in the right-to-right APU path. 8 8.1 8.1.1 APPENDIX Preliminary specification 3-line `L3' interface INTRODUCTION Table 34 The 3-lines common to all ICs; L3MODE, L3CLK and L3DATA SIGNAL MICROCONTROLLER SLAVE DEVICE input input input/output
The main purpose of the new interface definition is to define a protocol that allows for the transfer of control information and operational details between a microcontroller and a number of slave devices, at a rate that exceeds other common interfaces, but with a sufficient low complexity for application in consumer products. It should be clearly noted that the current interface definition is intended for use in a single apparatus, preferably restricted to a single printed circuit-board. The new interface requires 3 signal lines (apart from a return `ground') between the microcontroller and the slave devices (from this the name `L3' is derived). These 3-lines are common to all ICs connected to the bus: L3MODE, L3DATA and L3CLK. L3MODE and L3CLK are always driven by the microcontroller, L3DATA is bidirectional:
L3MODE(1) output L3CLK(2) L3DATA(3) Notes output output/input
1. L3MODE is used for the identification of the operation mode. 2. L3CLK is the bit clock to which the information transfer will be synchronized. 3. L3DATA will carry the information to be transferred. All slave devices in the system can be addressed using a 6-bit address. This allows for up to 63 different slave devices, as the all `0' address is reserved for special purposes. In addition it is possible to extend the number of addressable devices using `extended addressing'.
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
During operation 2 modes can be identified: 1. Addressing mode (AM).
SAA2501
During addressing mode a single byte is sent by the microcontroller. This byte consists of 2 data operation mode (DOM) bits and 6 operational address (OA) bits. Each of the slave devices evaluates the operational address. Only the device that has been issued the same operational address will become active during the following data mode. The operation to be executed during the data mode is indicated by the two data operation mode bits. 2. Data mode (DM). During data mode information is transferred between microcontroller and slave device. The transfer direction may be from microcontroller to slave (`write') or from slave to microcontroller (`read'). However, during one data mode the transfer direction cannot change.
8.1.1.1
Addressing mode
In order to start an addressing mode the microcontroller will make the L3MODE line LOW. The L3CLK line is put to the LOW state 8 times and the DATA line will carry 8 bits. The addressing mode is ended by making the L3MODE line HIGH.
handbook, halfpage
L3MODE
L3CLK
L3DATA
0
1
2
3
4
5
6
7
MGB505
The meaning of the bits on L3DATA. Bit 0 and bit 1; these are the data operation mode (DOM) bits that indicate the nature of the following data transfer. Each slave device may have its own allocation of operation modes to the 4 possible codes of these bits. For correct information about the operation the device will perform, refer to the descriptions of the individual ICs. For new designs the preferred allocations are given in Table 35. Bit 2 to bit 7; these bits act as 6 bit (special function) operational IC address, with bit 7 as MSB and bit 2 as LSB. Bit 7 to bit 5 act as system identification and bit 4 to bit 2 as identification of the device within the system.
Fig.16 Addressing mode.
Table 35 Preferred allocations DOM1 0 0 1 1 DOM0 0 1 0 1 FUNCTION data from microcontroller to SAA2501 data from SAA2501 to microcontroller control from microcontroller to SAA2501 status from SAA2501 to microcontroller REMARKS general purpose data transfer general purpose data transfer e.g. register selection for data transfer short device status message
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
8.1.1.2 Special function operational address
SAA2501
handbook, halfpage
L3MODE
L3CLK
L3DATA
0
1
2
3
4
5
6
7
MGB504
Fig.17 Data transfer mode.
Operational address 000000 (bit 2 to bit 7) is the special function address, and is used for the L3 device reset, as well as for the declaration and invalidation of the extended addressing. Both will be explained in Sections 8.1.2 and 8.1.3.
to indicate clearly whether or not the `halt mode' is necessary for correct operation of the interface. 8.1.2 DEVICE INTERFACE RESET
8.1.1.3
Data mode
In the data mode (see Fig.17) the microcontroller sends or receives information to or from the selected device. During data transfer the L3MODE line is HIGH. The L3CLK line is lowered 8 times during which the L3DATA line carries 8 bits. The information is presented LSB first and remains stable during the LOW phase of the L3CLK signal. The preferred basic data transfer unit is an 8 bit byte. Some implementations that are modifications of earlier circuits with 16 bit registers may use a basic unit of 16 bits, transferred as 2 bytes, with the most significant byte presented first. No other basic data transfer unit is allowed.
If the microcontroller sends an operational address `000000' with DOM1 and DOM0 also equal to `0' this indicates that none of the L3 interface devices is allowed to communicate with the microcontroller during the following data mode. This enables a different application of the L3CLK and L3DATA lines as the L3 devices will not interfere with any communication on these lines as long as L3MODE remains HIGH (e.g. the L3CLK and L3DATA lines are normally connected to USART circuits in the microcontrollers which allow for convenient communication between microcontrollers). Any addressing mode with a valid L3 operational address will re-enable the communication with the corresponding device. Devices with a fixed operational address (`Primary L3 devices') will react with a device reset condition regardless of the state of DOM1 and DOM0. Devices with a programmable operational address (`Secondary L3 devices') can only be put in the interface reset condition if the DOM1 and DOM0 bits are `0'. Other combinations of DOM1 and DOM0 initiate data transfers for `extended addressing'. 8.1.3 EXTENDED ADDRESSING
8.1.1.4
Halt mode
In between units the L3MODE line will be driven LOW by the microcontroller to indicate the completion of a basic unit transfer. This is called `halt mode' (HM). During halt mode the L3CLK line remains HIGH (to distinguish it from an addressing mode). The halt mode allows an implementation of an interface module without a bit counter. However, an implementation using a bit counter in the interface module may allow for the L3MODE line to be kept HIGH in between units (not using the halt mode). This implementation must also operate correctly if the halt mode is used. The documentation of the device will have January 1995 35
L3 Devices with a programmable address can be informed of their operational address using a special data transfer.
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
8.1.3.1 Operational address declaration
SAA2501
For the declaration (programming) of the operational address of an L3 device with a `secondary L3 identification code' the following actions are required: 1. First the microcontroller must issue an L3 operational address `000000' (special function address) with DOM1 = 0 and DOM0 = 1. This combination defines the operational address declaration operation. Next the microcontroller will start a data transfer mode in which it first sends the secondary L3 identification code for the device that is to be issued an operational address, followed by a byte containing the operational address (the DOM bits in this byte are don't cares). 2. Next the microcontroller will start a data transfer mode in which it first sends the secondary L3 identification code for the device that is to be issued an operational address, followed by a byte containing the operational address (the DOM bits in this byte are don't cares). A secondary L3 identification code is unique for any design. Devices of the same design have the same identification code of one or more bytes. However, special Table 36 Example of L3 devices; notes 1 to 4 ADDRESSING MODE SPECIAL ADDRESS BYTE 1 10000000 Notes 1XXXXXXX
designs may have a range of identification codes, one of which can be selected by a hardware solution, to enable the connection of more than one device of the same design to the L3 interface. It is also possible to use separate L3MODE lines for multiple devices of the same design, but the same L3 identification code (this also enables `parallel programming' of these devices). Bit 0 of any identification code byte will indicate whether or not an additional byte follows: Bit 0 = 0; no additional byte as part of the identification code. Bit 0 = 1; additional byte follows. With this the number of secondary L3 identification codes is (theoretically) unlimited. The operational address for the programmable device is preferable in the range 111000 to 111111. However, it is possible in a given application to issue any operational address that is not used to address primary L3 devices or other secondary L3 devices. An example is given in Table 36.
DATA MODE SECONDARY L3 IDENTIFICATION CODE BYTE 2 1XXXXXXX BYTE 3 0XXXXXXXX OPERATIONAL ADDRESS (ONE BYTE) MMYYYYYY
1. Bits are shown in the order they appear on L3DATA (bit 0 first, bit 7 last). 2. X = bit of the identification code. 3. M = DOM bit of operational address (don't care). 4. Y = bit of the operational address.
8.1.3.2
Operational address invalidation
In order to re-allocate an operational address that has been allocated to a secondary L3 device it is possible to invalidate an operational address: * First the microcontroller must issue an L3 operational address `000000' (special function address) with DOM1 = 1 and DOM0 = 0. This combination defines the operational address invalidation operation. * Next the microcontroller will start a data transfer mode in which it only sends the secondary L3 identification code for the device that will no longer be addressed. From this moment on the device will not be able to communicate with the microcontroller until it is issued a new operational address by an OA declaration (it will enter a `device interface reset' condition). Remark: the combination of a special function address (000000) and DOM1 and DOM0 equal to `1' is reserved for future applications. Designs based on this specification will react with a `device interface reset'.
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
8.1.4 EXAMPLE OF A DATA TRANSFER
SAA2501
handbook, full pagewidth
L3MODE
L3CLK (1)
L3DATA
(2)
address
data byte 1
data byte 2
data byte 3
data byte 4
address
MGB506
(1) L3CLK is triggered by L3MODE. (2) For more details (see Fig.20).
Fig.18 Example of transfer of 4 bytes. A data transfer starts when the microcontroller sends an address on the bus. All ICs will evaluate this address, but only the IC addressed will be an active partner for the microcontroller in the following data transfer mode. During the data transfer mode bytes will be sent from or to the microcontroller. In this example the L3MODE line is made LOW (`halt mode') in between byte transfers. This is the default operation, although some ICs may allow the L3MODE line to be kept HIGH. This exception must be specified clearly in the IC documentation, and such ICs must be able to communicate with microcontrollers that make L3MODE LOW in between transfers. It is suggested that new designs only use bytes as basic data transfer units. After the data transfer the microcontroller does not need to send a new address until a new data transfer is necessary. Alternatively it may also send the `special address' 000000 to indicate the end of the data transfer operation. 8.1.5 TIMING REQUIREMENTS
These are requirements for the slave devices designed according to the 'L3' interface definitions.
8.1.5.1
Addressing mode
handbook, full pagewidth
t d1 L3MODE t cL t cH
t h2
L3CLK
L3DATA t su t h1
MGB507
Fig.19 Addressing mode timing.
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
Table 37 Requirements for addressing mode timing (see Fig.19) SYMBOL td1 tcL tcH tsu1 th1 th2 L3CLK LOW time L3CLK HIGH time L3DATA set-up time before L3CLK HIGH L3DATA hold time after L3CLK HIGH L3CLK hold time before L3MODE HIGH PARAMETER L3CLK HIGH to L3CLK LOW delay time after L3MODE LOW
SAA2501
REQUIREMENT 190 250 250 190 30 190 ns ns ns ns ns ns
UNIT
8.1.5.2
Data mode
t d1 L3MODE t cL L3CLK t su L3DATA microcontroller to IC L3DATA IC to microcontroller t d2 t d3 t h3 t d4 t d5
MGB508
andbook, full pagewidth
t h2
t cH
t h1
Fig.20 Data mode timing.
Table 38 Requirements for data mode timing (see Fig.20) SYMBOL td1 tcL tcH tsu1 th1 th2 td2 td3 th3 td4 td4 td5 January 1995 L3CLK LOW time L3CLK HIGH time PARAMETER L3CLK HIGH to L3CLK LOW delay time after L3MODE HIGH REQUIREMENT 190 250 250 190 30 190 0 < td2 50 380 50 360 530 0 < td5 50 38 ns ns ns UNIT
Microcontroller to slave device L3DATA set-up time before L3CLK HIGH L3DATA hold time after L3CLK HIGH L3CLK hold time before L3MODE HIGH ns ns ns
Slave device to microcontroller L3DATA enable time after L3MODE HIGH L3DATA stable time after L3MODE HIGH L3DATA hold time after L3CLK HIGH L3DATA stable time after L3CLK HIGH L3DATA stable time after L3CLK HIGH between bit 7 of a byte and bit 0 of next byte if no halt mode is used L3DATA disable time after L3MODE LOW ns ns ns ns ns ns
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
8.1.5.3 Halt mode
SAA2501
handbook, full pagewidth
tL L3MODE t h2 L3CLK td5 L3DATA IC to microcontroller
MGB509
t d1
t d2
Fig.21 Halt mode timing.
Table 39 Requirements for halt mode timing (see Fig.21) SYMBOL td1 tL th2 td2 td5 8.2 L3MODE LOW time L3CLK hold time before L3MODE LOW PARAMETER L3CLK HIGH to L3CLK LOW delay time after L3MODE HIGH REQUIREMENT 190 190 190 0 < td2 50 0 < td5 50 ns ns ns UNIT
Slave device to microcontroller L3DATA enable time after L3MODE HIGH L3DATA disable time after L3MODE LOW SAA2501 L3 protocol enhancement options ns ns
The L3 interface on the SAA2501 is limited in speed, dictated both by the maximum SAA2501 handling speed and the upper frequencies of the L3 interfacing standard. On the other hand, the SAA2501 offers several enhancements to make a better use of the SAA2501 L3 interface capacity. The enhancements are optional. The applicant chooses whether to use them or not. 8.2.1 TESTING L3RDY BY POLLING L3DATA
the status byte can be transferred. To avoid these status byte transfers (thus reducing the host's load), after writing the SAA2501 `read status' operational address, L3RDY is continuously copied to signal L3DATA during the period in which no L3 transfers (i.e. status byte readings) are performed. Meanwhile, L3MODE must be kept HIGH (no L3 operational addresses may be written). As a result, L3RDY can be tested as shown in Table 40.
The host must test status flag L3RDY to make sure whether the SAA2501 L3 interface is ready to transfer data item bytes. According to the general protocol, described in Section 7.20.6, the status is read by first writing the SAA2501 `read status' operational address, after which
January 1995
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
Table 40 Testing L3RDY by polling L3DATA; note 1 L3DATA 01100011 polled Note 1. No status byte transfers are needed; the load of the host (microcontroller) can thus be reduced. 8.2.2 OPTIONS TO INCREASE THE TIMING ACCURACY OF APU COEFFICIENT WRITING TRANSFER SOURCE host SAA2501 L3MODE 0 1 EXPLANATION write `read status' operational address test L3DATA; repeat this step until L3DATA = 1
SAA2501
THE
The SAA2501 offers three enhancements to increase the timing accuracy with which APU coefficients can be updated by the application: 1. Status polling is not required when APU coefficients are written. L3 status flag L3RDY, when read anyhow, will always be HIGH, indicating that the next APU coefficient transfer may be done. The transfer speed is only limited by the maximum allowed frequency of L3CLK. As a result, also no `write item data' operational address is needed any more before writing each APU coefficient index. 2. Normally, no more bytes may be written to a writeable data item than the length of that specific item. An exception is formed by the APU coefficients. They may be written continuously with a coefficient wrap. After the writing of all 4 coefficients, the writing can be continued at the first APU coefficient without having to write a new control byte. 3. The data item transfer protocol, described in Section 7.20.6, although transparent, allows only for the reading or writing of data items from their first data byte onwards. This approach can lead to situations where e.g. 54 Ancillary Data item bytes must all be read (which takes at least 54 x 200 s = 10.8 ms, due to the interface speed limitations: see Section 7.20.6) before the next data item can be transferred. The SAA2501 enables the writing of APU coefficients without having to wait for the current item transfer to finish. In order to do so, a running transfer can be interrupted by an APU coefficient write transfer, and then be resumed with the `continue current transfer' control byte. An item transfer may be interrupted at any time to write APU coefficients. After the `continue previous transfer' control byte, a operational address must always follow, indicating the type of L3 transfer that will follow. An APU coefficient write transfer itself cannot be interrupted.
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
SAA2501
The 3 mentioned options are all illustrated in Table 41, where a data item transfer is interrupted between the reading of the nth and (n + 1)th data item byte. Table 41 Example of 3 options to increase the timing accuracy of the APU coefficient writing L3DATA(1) DDDDDDDD 01100010 00000110 01100000 DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD DDDDDDDD 01100010 00000111 01100011 SSSSSSSS 01100001 DDDDDDDD etc. Note 1. Explanation of bytes: a) DDDDDDDD = data byte. b) SSSSSSSS = status byte. TRANSFER SOURCE SAA2501 host host host host host host host host host host host host host host SAA2501 host SAA2501 etc. L3MODE 1 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 etc. read nth item data byte indicate `write control' transfer write `write APU coefficients' control byte indicate `write item data' transfer write APU coefficient LL write APU coefficient LR write APU coefficient RL write APU coefficient RR write APU coefficient LL write APU coefficient LR write APU coefficient RL write APU coefficient RR indicate `write control' transfer write `continue previous transfer' control byte indicate `read status' transfer read status; repeat this step until L3RDY = 1 indicate `read item data' transfer read (n + 1)th item data byte etc. EXPLANATION
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDD VI IDD II IO Ptot Tstg Tamb Ves1 Ves2 Notes 1. Input voltage should not exceed 6.5 V unless otherwise specified. 2. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 3. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. PARAMETER supply voltage input voltage supply current input current output current total power dissipation storage temperature operating ambient temperature electrostatic handling electrostatic handling note 2 note 3 2 mA outputs 4 mA outputs VDD = 5 V5% note 1 CONDITIONS MIN. -0.5 -0.5 - - - - - -65 -40 -2000 -200 MAX. +6.5 VDD + 0.5 100 10 10 20 165 +150 +85 +2000 +200
SAA2501
UNIT V V mA mA mA mA mW C C V V
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
10 DC CHARACTERISTICS VDD = 5 V 10%; Tamb = -40 to +85 C; unless otherwise specified SYMBOL Supply IDD VIH VIL VIH VIL VtLH VtHL Vhys |II| Rpull Outputs VOH VOL |IOZ| Notes HIGH level output voltage LOW level output voltage 3-state OFF-state leakage current IO = 4 mA IO = 4 mA VDD - 0.5 - - - - - - quiescent supply current note 1 100 - - - - - - - 0.3VDD - - - PARAMETER CONDITIONS MIN. TYP.
SAA2501
MAX.
UNIT A
Inputs; notes 2 and 3 HIGH level input voltage (CMOS) LOW level input voltage (CMOS) HIGH level input voltage (TTL) LOW level input voltage (TTL) positive going threshold voltage (CMOS Schmitt trigger) negative going threshold voltage (CMOS Schmitt trigger) hysteresis voltage (CMOS Schmitt trigger) input current pull-up resistor 0.7VDD 0 2 0 - 0.2VDD - - 14 VDD 0.3VDD VDD 0.8 0.8VDD - - 5 140 V V V V V V V A k
V V A
0.5 5
1. TDI, TMS, TRST and L3DATA not driven; TC0 and TC1 driven HIGH; all other inputs driven LOW. 2. Inputs TRST, TCK, TMS and TDI are TTL level compatible; all other inputs are CMOS level compatible. 3. Input TRST (pin 38) should be connected to ground for normal operation and connected to VDD for boundary scan testing.
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Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
11 AC CHARACTERISTICS VDD = 5 V 10%; Tamb = -40 to +85 C; unless otherwise specified SYMBOL Clocks Ci MCLKIN fclk tr tf tH tL X22IN fclk tr tf tH tL FSCLKIN fclk tr tf tH tL CDSCL fclk tr tf tH tL CDMCL fclk clock frequency note 2 - 1 ---------8T m - - - clock frequency rise time fall time HIGH time LOW time note 1 note 1 note 2 note 2 - - - Tm + 20 Tm + 20 - 12 12 - - clock frequency rise time fall time HIGH time LOW time FSCLK384 = 1 FSCLK384 = 0 note 1 note 1 - - - - 12 12 384fs 256fs 5 5 - - - - - - - - clock frequency rise time fall time HIGH time LOW time - - - 12 12 22.579 12 12 - - - - - - - clock frequency rise time fall time HIGH time LOW time MCLK24 = 1 MCLK24 = 0 - - - - 12 12 24.576 12.288 12 12 - - - - - - - - input capacitance - - 10 PARAMETER CONDITIONS MIN. TYP.
SAA2501
MAX.
UNIT
pF
MHz MHz ns ns ns ns
MHz ns ns ns ns
Hz Hz ns ns ns ns
768 - - - -
kHz ns ns ns ns
Hz
L3CLK tH tL HIGH time LOW time Tm + 10 Tm + 10 - - ns ns
January 1995
44
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
SAA2501
SYMBOL FSCLK fclk
PARAMETER
CONDITIONS -
MIN.
TYP. -
MAX.
UNIT
clock frequency
MSEL = 00; FSCLKM = 0; fs = 44.1 kHz MSEL = 00; FSCLKM = 0; fs = 48 kHz MSEL = 00; FSCLKM = 0; fs = 32 kHz
1
2fX22IN
MHz
-
1
2fMCLKIN
-
MHz
-
1
3fMCLKIN
-
MHz
MCLK fclk SCK fclk clock frequency FSCLK384 = 0; fSCK = 64fs FSCLK384 = 1; fSCK = 64fs Inputs Ci tsu1 tsu2 input capacitance set-up time FDAI to SCK HIGH set-up time CDM and CDMEF to CDMCL, CDS, CDSEF and CDSWA HIGH set-up time CDSSY to CDSCL HIGH delay time L3MODE to L3LCK LOW hold time FDAI to SCK HIGH hold time CDM, CDMEF to CDMCL, CDS, CDSEF and CDSWA HIGH hold time CDSSY to CDSCL HIGH input hold time L3MODE LOW time CL < 25 pF CL < 25 pF - 33 42 - - - 10 - - pF ns ns - -
1 1 4fSCLK 6fSCLK
clock frequency
-
fMCLKIN
- - -
MHz
MHz MHz
tsu3 td1 th1 th2 th3 th4 tL Outputs Co th th td td
Tm + 10 0 0 0 10 0 Tm + 10 - notes 3 and 4 notes 3 and 4 -22 -15 - -
- - - - - - - - - - - -
- - - - - - -
ns ns ns ns ns ns ns
output capacitance hold time SD, WS, FDAO, FDFSY and FDEF to SCK LOW hold time CDMWS to CDMCL LOW
50 - - 10 0
pF ns ns ns ns
delay time SD, WS, FDAO, FDFSY and note 3 FDEF to CDMCL LOW delay time CDMWS to CDMCL LOW note 3
January 1995
45
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
SAA2501
SYMBOL Inputs/outputs Co tsu th th td td2 td3 td5 Notes
PARAMETER
CONDITIONS - note 5 note 5 notes 3 and 5 notes 3 and 5 notes 3 and 6 notes 3 and 6 note 3
MIN. - - - - - - - -
TYP.
MAX.
UNIT
output capacitance input set-up time input hold time output hold time output delay time 3-state enable time 3-state stable time 3-state disable time L3DATA to L3MODE LOW
50 - - - 2Tm + 30 20 20 20
pF ns ns ns ns ns ns ns
Tm + 10 10 Tm - - - -
1. Short rise and fall times improve the tolerance of clocks to signal and supply noise. 4 2 2. If MCLK24 = 1 then T m = ------------------- else T m = ------------------- . f MCLKIN f MCLKIN 3. To allow for the effects of load capacitance the timing values should be de-rated by 0.5 ns/pF. 4. For maximum clock signal load of 25 pF. 5. L3DATA to L3CLK HIGH. 6. L3DATA to L3MODE HIGH.
January 1995
46
X22IN
MCLKIN
GND1
V DD1
MCLK
FSCLKIN
FSCLK
X22OUT
STOP 12 13 14 15 16 MPEG slave interface 17 18 19 20 21 22 URDA CDMWS CDMEF CDM CDMCL GND2 CDSCL CDS CDSEF
MCLKOUT
L3MODE
L3DATA
GND3
FDEF
FDAI
SCK
CDSSY L3CLK
FDAO
WS
SD
handbook, full pagewidth
January 1995
RESET FS256 MPEG master interface CLOCK CIRCUIT C 11 10 9 8 7 6 5 4 3 2 1 RESET MCLK24 FSCLKM FSCLK384 TDI TMS 44 43 42 41 40 39 38 37 36 5V 5V C C 8 9 10 11 12 13 14 4 5 6 7 5V C 2 3 5V R 4.7 H 1 5V (1)
12 APPLICATION INFORMATION
Philips Semiconductors
Digital Audio Broadcast (DAB) decoder
TDA1305 DAC
V DDA V SSA TEST1 BCK WS DATA CLKS1 CLKS2 VSSD VDDD TEST2 V DDO V SSO V ref VOR FILTCR FILTCL VOL ATSB DSMB MUSB DEEM2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 5V
MBE115
5V
C
1 F 1 k 10 k 10 k 1 k
C
100 F
1 nF 1 nF
right output
SAA2501
TCK TRST TDO TC0
47
100 F
left output
CDSWA
35 TC1 VDD2 34 FDFSY
L3 bus
23 24 25 26 27 28 29 30 31 32 33 R R R
SYSCLKI DEEM1 n.c. n.c. SYSCLKO VSSD
Preliminary specification
SAA2501
C = 100 nF; R = 47 .
Fig.23 Typical application diagram.
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
13 PACKAGE OUTLINE
SAA2501
handbook, full pagewidth
seating plane
0.1 S
S
12.9 12.3 44 1 34 33 1.2 (4x) 0.8 B
pin 1 index 0.8
11 12 0.40 0.20 10.1 9.9 22
23
0.40 0.20
0.15 M A
1.2 (4x) 0.8
0.15 M B
10.1 9.9
12.9 12.3
X
0.8
A
0.85 0.75 1.85 1.65 0.25 0.05 0.25 0.14 2.10 1.70
MBB944 - 2
detail X
0.95 0.55
0 to 10 o
Dimensions in mm.
Fig.24 Plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm (QFP44; SOT307-2).
January 1995
48
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
14 SOLDERING 14.1 14.1.1 Plastic quad flat-packs BY WAVE
SAA2501
applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. 14.1.3 REPAIRING SOLDERED JOINTS (BY HAND-HELD
SOLDERING IRON OR PULSE-HEATED SOLDER TOOL)
During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. 14.1.2 BY SOLDER PASTE REFLOW
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be
15 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
January 1995
49
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
NOTES
SAA2501
January 1995
50
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
NOTES
SAA2501
January 1995
51
Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., 6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)428 6729 India: Philips INDIA Ltd, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5028, Fax. (03)3740 0580 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546. Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366. Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382. Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319. Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (081)730-5000, Fax. (081)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD36 (c) Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
513061/1500/01/pp52 Document order number: Date of release: January 1995 9397 746 40011
Philips Semiconductors

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